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crawfxrd
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From Table 7. Host Device ID (DID0) and Process Graphics Device ID (DID2): > Note: 1. DID2 value depends on graphics cores and platform > configuration. Default value for 12xe graphics is B080h. > Optional values are: > * B081 > * B082 > * B083 > * B08F > Refer to Panther Lake GPU Dynamic Branding Technical Advisory (#851572). Fixes graphics init on Clevo L240JUX, which has DID 0xb082. Change-Id: I5354b53ebe7f2c02db3557a26f2b978b98a6390f Ref: Core Ultra Series 3 EDS, Volume 1 (#815002, r2.2) Signed-off-by: Tim Crawford <tcrawford@system76.com>
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Not sure what's causing this dmesg error: And some warnings: |
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12.4.5 Package C-States:
> The processor supports C0, C2, C6, and C10 package states.
Fixes Linux kernel warning:
[Firmware Bug]: ACPI MWAIT C-state 0x33 not supported by HW (0x1000)
Change-Id: I31b2da7c277fe963145b41d4f5809854ee66c13e
Ref: Core Ultra Series 3 EDS, Volume 1 (#815002, r2.2)
Signed-off-by: Tim Crawford <tcrawford@system76.com>
There are 2 variants as they use different EC firmware based on the keyboard. - lemp14: 14" model with 83 key keyboard - lemp14-b: 16" model with 102 key keyboard Change-Id: Id8b0b3bf0591c49f5b2b284ea1ed4fe17a4305b3 Co-authored-by: Tim Crawford <tcrawford@system76.com> Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: If62fd5fc033b6dbeba1b74e9f4fc27f5f0ef40e2 Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: Ib03096f05ed1500b935087a346b9bde8fe80c4fa Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I510ada5e27eabae04ccbe36d548f5c652ee29cd2 Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I1fc3c5fb8e7d8e8423a80179fe4e29c403e5a110 Signed-off-by: Tim Crawford <tcrawford@system76.com>
From 2.3 Pin Descriptions: > The Chip Select# and I/O[n:0] pins require weak pull-up to be enabled > on these pins whereas the Serial Clock requires a weak pull-down. This matches our other boards, except MTL which is also misconfigured. Ref: eSPI Base Specification r1.6 (#841685) Change-Id: I34c2f8c7c3e1628ee213ea11c94dbc7b0aa19039 Signed-off-by: Tim Crawford <tcrawford@system76.com>
- Requires CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 and CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1 flags. - The existing static gpe functions has been renamed with gpe0. - Add gpe1 functions. BUG=b:362310295 TEST=Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 and CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1 flags, boot google/fatcat or intel/ptlrvp DUT, and check if GPE1 sts bits have been printed during boot. Search for: [DEBUG] GPE1 STD STS: <event string> Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d
New GPE1 bits are introduced in PTL for internal devices, including PME_B0, hot plug, and PCIe events. defines for GPE number for additional STD GPE0 in PTL defines for GPE number for GPE1 defines for GPE1 bits SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is selected NOTE: All GEP1 bits are STD (Intel's Standard) GPE bits. BUG=362310295 TEST=This cannot be tested directly. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836
This change is to add the required GPE1 override functions for PTL. The override functions are called in Intel common pmclib.c. NOTE that GPE1 bits are SOC-specific and they are related to GPE0 events. 1. When CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is set, the SOC GPE1 override functions soc_pmc_disable_std_gpe1() and soc_pmc_enable_std_gpe1() are required in order to configure GPE1 bits properly according to the corresponding GPE0 bits. 2. The mapping for GPE1 bits to their readable string is also provided BUG=b:362310295 TEST=This cannot be tested directly. Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 in google/fatcat or inte/ptlrvp. Boot to OS, Check both GPE0 and GPE1 EN bits. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia79c49d399eff4b2f6978323b2f5e2bb167d8638
Change-Id: I0c7b8b09364e0b7cf9800dca6bcd91750f68a142 Signed-off-by: Tim Crawford <tcrawford@system76.com>
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Reopen #268 because GitHub won't let me change the base branch.